The present invention relates to a semiconductor device, such as an insulated gate metal oxide semiconductor field-effect transistor (MOSFET), an insulated gate bipolar transistor (OGBT), a bipolar transistor and a diode, which has a special longitudinal structure composed of a parallel pn layer that conducts electricity in the ON state and is depleted in the OFF state.
A high resistance layer between two electrodes provided on opposite two principal faces must be thick in order to achieve a high withstand voltage in a longitudinal semiconductor device, in which an electric current flows between the two electrodes. A device having the thick high resistance layer provides high ON-state resistance between the two electrodes, and thus, the loss is unavoidably increased. In short, there is a trade-off relationship between the ON-state resistance (the current-carrying capacity) and the withstand voltage. As is well known, the trade-off relationship applies to a variety of semiconductor devices such as an IGBT, a bipolar transistor and a diode. The problem also applies to a lateral semiconductor device in that a direction in which a drift current flows in the ON state is different from a direction in which a depletion layer spreads due to the reverse bias in the OFF state.
To address the above-mentioned problem, European Patent No. 0,053,854, U.S. Pat. No. 5,216,275, U.S. Pat. No. 5,438,215, and Japanese Patent Provisional Publication No. 9-266311 developed by the inventors of this invention have disclosed a semiconductor device having a drift layer composed of a parallel pn layer, in which n regions and p regions with high impurity density are alternately piled up. In this semiconductor device, the parallel pn layer is depleted in the OFF state to endure the withstand voltage.
FIG. 10 is a partial sectional view showing the longitudinal MOSFET according to a preferred embodiment of the U.S. Pat. No. 5,216,275. This MOSFET is characterized in that a drift layer 12, which is the single layer in the normal longitudinal semiconductor device, is a parallel pn layer composed of n drift regions 12a and p partition regions 12b. Reference numeral 13a denotes p well regions; numeral 13b denotes p+ contact regions; numeral 14 denotes n+ source regions; numeral 15 denotes a gate insulating film; numeral 16 denotes gate electrodes; numeral 17 denotes source electrodes; and numeral 18 denotes drain electrodes.
In the drift layer 12, for example, a high resistance n-type layer is grown by an epitaxial method, and trenches extending to the n+ drain layers are selectively etched to form the n drift regions 12a. Then, a p-type layer is grown in the trench by the epitaxial method to form the p partition regions 12b. 
In the following description, a semiconductor device having a drift layer composed of a parallel pn layer, which conducts electricity in the ON state and is depleted in the OFF state, will be referred to as a super-junction semiconductor device.
The above-mentioned publications only describe the drift layer composed of the parallel pn layer, which conducts electricity, and fails to mention any voltage withstand structure for achieving the high withstand voltage provided at the periphery of the semiconductor device. If there is only provided the drift layer composed of the parallel pn layer without any voltage withstand structure, it is impossible to achieve the high withstand voltage.
Examples of the voltage withstand structure are a guard ring and a field plate. The semiconductor device should have a suitable structure for having the guard ring and the field plate. In this case, it is necessary to perform the process such as forming a mask, implanting and diffusing impurities, or coating and patterning metal film.
In view of the foregoing, it is an object of the present invention to provide a super-junction semiconductor device, which improves the trade-off relationship between the ON-resistance and the withstand voltage and easily achieves a high withstand voltage.
To achieve the above-mentioned object, the present invention is directed to a super-junction semiconductor device, which comprises first and second principal faces, electrodes provided on the principal faces, a low resistance layer between the first and second principal faces, and a parallel pn layer, in which first-conductivity-type drift regions and second-conductivity-type partition regions are arranged alternately, the parallel pn layer being provided between the two principal electrodes and conducting electricity in the ON state and being depleted in the OFF state, wherein a first-conductivity-type or second-conductivity-type high resistance region is formed at the periphery of the parallel pn layer
A depletion layer spreads into the high resistance region formed at the periphery of the parallel pn layer when a reverse voltage is applied. This achieves the high withstand voltage. Particularly, if the withstand voltage of the super-junction semiconductor device is VDSS (V), the impurity density ND of the nxe2x88x92 high resistance region is 5.62xc3x971017xc3x97VDSSxe2x88x921.36(cmxe2x88x923) or less.
As described later in detail, if the density is as low as 5.62xc3x971017xc3x97VDSSxe2x88x921.36(cmxe2x88x923) or less, the depletion layer can spread satisfactorily even if there is provided no conventional guard ring structure, or the like. Consequently, the semiconductor device can have the high withstand voltage. Of course, it is possible to provide the device with the guard ring structure.
A low resistance region of the same conductivity type as the high resistance region is formed at the periphery of the high resistance region. The low resistance region connects to a low resistance layer formed below the semiconductor substrate.
A low resistance region of the same conductivity type as the high resistance region is formed at the periphery of the high resistance region. The low resistance region is used as channel stoppers to thereby decrease the leakage current.
An insulating film is formed on surface of the high resistance region in order to protect and stabilize the surfaces.
In the simplest structure, the sides of the semiconductor chip are covered with the low resistance region.
If first-conductivity-type high resistance region is formed at the periphery of the parallel pn layer, a net quantity of impurities in an outermost second-conductivity-type partition region is substantially equal to a net quantity of impurities in each region of the parallel pn layer inside the outermost partition region. If second-conductivity-type high resistance region is formed at the periphery of the parallel pn layer, a net quantity of impurities in an outermost first-conductivity-type drift region is substantially equal to a net quantity of impurities in each region of the parallel pn layer inside the outermost drift region.
Each region of the parallel layer pn inside the outermost region is sandwiched between the regions of the opposite conductivity type with substantially the same impurity density, and one side of the outermost region is in contact with the high resistance region. For this reason, the quantity to be compensated by the impurities of the opposite conductivity type is decreased, and this increases the net quantity of impurities. This results in the unbalanced depletion, and lowers the withstand voltage. In order to achieve the high withstand voltage, the net quantity of impurities in the outermost region is substantially equal to the net quantity of impurities in each region of the parallel pn layer inside the outermost region.
If first-conductivity-type high resistance region is formed at the periphery of the parallel pn layer, a net quantity of impurities at an end of a second-conductivity-type partition region at a corner part must be substantially equal to a net quantity of impurities in each of the parallel pn layer. If second-conductivity-type high resistance region is formed at the periphery of the parallel pn layer, a net quantity of impurities at an end of a first-conductivity-type drift region at a corner part is substantially equal to a net quantity of impurities in each of the parallel pn layer.
In a method for manufacturing the above-mentioned super-junction semiconductor device, an ion implantation area in an outermost second-conductivity-type partition region is set as being smaller than an ion implantation area in each region of the parallel pn layer inside the outermost partition region, and a net quantity of impurities in the outermost second-conductivity-type partition region is set as being substantially equal to a net quantity of impurities in each region of the parallel pn layer inside the outermost partition region.
The quantity of impurities in the outermost second-conductivity-type drift regions is controlled in the above-mentioned manner.
The outermost first-conductivity-type partition regions are controlled in the same manner.